Chein-Wei Jen: search on Z-Library

Fundraising September 15, 2024 – October 1, 2024 About fundraising

The world's largest scientific articles store. 70,000,000+ articles for free.

Fundraising September 15, 2024 – October 1, 2024

Z-Library is one of the largest online libraries in the world that contains over 17,000,000 books and 84,837,000 articles. We aim to make literature accessible to everyone. Today (September 15, 2024) we've started additional fundraising to project maintenance and development.

Also UNLIMITED downloads (for 31 days after the day of making donation) are available for ALL contributors who will donate during the fundraising period till October 1, 2024.

About fundraisingRead more

Make a donation

1

High-speed and low-power split-radix FFT

Wen-Chang Yeh, Chein-Wei Jen

Journal:

IEEE Transactions on Signal Processing

Year:

2003

Language:

english

File:

PDF, 787 KB

english, 2003

2

On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture

Jen-Chieh Tuan,, Tian-Sheuan Chang,, Chein-Wei Jen,

Journal:

IEEE Transactions on Circuits and Systems for Video Technology

Year:

2002

Language:

english

File:

PDF, 283 KB

english, 2002

3

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization

Kun-Bin Lee,, Hui-Cheng Hsu,, Chein-Wei Jen,

Year:

2004

Language:

english

File:

PDF, 276 KB

english, 2004

4

A new hardware-efficient architecture for programmable FIR filters

Hwan-Rei Lee,, Chein-Wei Jen,, Chi-Min Liu,

Journal:

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing

Year:

1996

Language:

english

File:

PDF, 906 KB

english, 1996

5

[IEEE 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation - Taipei, Taiwan (20-22 Oct. 1999)] 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) - A compact IDCT processor for HDTV applications

Tian-Sheuan Chang,, Jiun-In Guo,, Chein-Wei Jen,

Year:

1999

Language:

english

File:

PDF, 321 KB

english, 1999

6

[IEEE ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems - Sydney, NSW, Australia (6-9 May 2001)] ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) - An efficient 2-D DWT architecture via resource cycling

Tay-Jyi Lin,, Chein-Wei Jen,

Year:

2001

Language:

english

File:

PDF, 382 KB

english, 2001

7

[IEEE ISCAS 2003. International Symposium on Circuits and Systems - Bangkok, Thailand (25-28 May 2003)] Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. - Area-effective FIR filter design for multiplier-less implementation

Tay-Jyi Lin,, Tsung-Hsun Yang,, Chein-Wei Jen,

Year:

2003

Language:

english

File:

PDF, 307 KB

english, 2003

8

[IEEE 2002 IEEE International Symposium on Circuits and Systems - Phoenix-Scottsdale, AZ, USA (26-29 May 2002)] 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) - High-speed memory-saving architecture for the embedded block coding in JPEG2000

Yun-Tai Hsiao,, Hung-Der Lin,, Kun-Bin Lee,, Chein-Wei Jen,

Year:

2002

Language:

english

File:

PDF, 352 KB

english, 2002

9

Hardware-efficient DFT designs with cyclic convolution and subexpression sharing

Tian-Sheuan Chang,, Jiun-In Guo,, Chein-Wei Jen,

Journal:

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing

Year:

2000

Language:

english

File:

PDF, 174 KB

english, 2000

10

[IEEE 2005 IEEE International Symposium on Circuits and Systems - Kobe, Japan (23-26 May 2005)] 2005 IEEE International Symposium on Circuits and Systems - Pipelining Technique for Energy-Aware Datapaths

Wei-Sheng Huang,, Tay-Jyi Lin,, Shih-Hao Ou,, Chih-Wei Liu,, Chein-Wei Jen,

Year:

2005

Language:

english

File:

PDF, 237 KB

english, 2005

11

[IEEE The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. - Tainan, Taiwan (Dec. 6-9, 2004)] The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. - Complexity-aware design of da-based FIR filters

Chih-Chao Chen,, Tay-Jyi Lin,, Chih-Wei Liu,, Chein-Wei Jen,

Year:

2004

Language:

english

File:

PDF, 286 KB

english, 2004

12

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - Static floating-point unit with implicit exponent tracking for embedded DSP

Hung-Yueh Lin,, Tay-Jyi Lin,, Chie-Min Chao,, Yen-Chin Liao,, Chih-Wei Liu,, Chein-Wei Jen,

Year:

2004

Language:

english

File:

PDF, 257 KB

english, 2004

13

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding

Kun-Bin Lee,, Jih-Yiing Lin,, Chein-Wei Jen,

Year:

2004

File:

PDF, 262 KB

2004

14

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding

Kun-Bin Lee,, Jih-Yiing Lin,, Chein-Wei Jen,

Year:

2004

Language:

english

File:

PDF, 262 KB

english, 2004

15

[IEEE ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems - Sydney, NSW, Australia (6-9 May 2001)] ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) - Power modeling and low-power design of content addressable memories

Ilion Yi-Liang Hsiao,, Ding-Hao Wang,, Chein-Wei Jen,

Year:

2001

Language:

english

File:

PDF, 426 KB

english, 2001

16

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - QME: an efficient subsampling-based block matching algorithm for motion estimation

Kun-Bin Lee,, Hao-Yun Chin,, Hui-Cheng Hsu,, Chein-Wei Jen,

Year:

2004

Language:

english

File:

PDF, 298 KB

english, 2004

17

[Presses Polytech. Univ. Romandes ISCAS 2000 Geneva. 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings - Geneva, Switzerland (28-31 May 2000)] 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) - Motion estimation using on-line arithmetic

Ching-Long Su,, Chein-Wei Jen,

Year:

2000

Language:

english

File:

PDF, 467 KB

english, 2000

18

[IEEE 2007 IEEE International Symposium on Circuits and Systems - New Orleans, LA, USA (2007.05.27-2007.05.30)] 2007 IEEE International Symposium on Circuits and Systems - Latency-Tolerant Virtual Cluster Architecture for VLIW DSP

Hsiao, Pi-Chen, Lin, Tay-Jyi, Liu, Chih-Wei, Jen, Chein-Wei

Year:

2007

Language:

english

File:

PDF, 603 KB

english, 2007

19

[IEEE ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems - Sydney, NSW, Australia (6-9 May 2001)] ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) - Arbitrarily scalable edge-preserving interpolation for 3-D graphics and video resizing

Yuan-Chung Lee,, Chein-Wei Jen,

Year:

2001

Language:

english

File:

PDF, 548 KB

english, 2001

20

[IEEE 2002 IEEE International Symposium on Circuits and Systems - Phoenix-Scottsdale, AZ, USA (26-29 May 2002)] 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) - CASCADE - configurable and scalable DSP environment

Tay-Jyi Lin,, Chein-Wei Jen,

Year:

2002

Language:

english

File:

PDF, 344 KB

english, 2002

21

[Presses Polytech. Univ. Romandes ISCAS 2000 Geneva. 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings - Geneva, Switzerland (28-31 May 2000)] 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) - A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routers

Ilion Yi-Liang Hsiao,, Chein-Wei Jen,

Year:

2000

Language:

english

File:

PDF, 383 KB

english, 2000

22

[Presses Polytech. Univ. Romandes ISCAS 2000 Geneva. 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings - Geneva, Switzerland (28-31 May 2000)] 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) - Deferred lighting: a computation-efficient approach for real-time 3-D graphics

Bor-Sung Liang,, Wen-Chang Yeh,, Yuan-Chung Lee,, Chein-Wei Jen,

Year:

2000

Language:

english

File:

PDF, 358 KB

english, 2000

23

Multi-dimensional parallel computing structures for regular iterative algorithms

Chein-Wei Jen, Ding-Ming Kwai

Journal:

Integration, the VLSI Journal

Year:

1989

Language:

english

File:

PDF, 438 KB

english, 1989

24

A motion detection scheme for motion adaptive pro-scan conversion

Shifan Chang, Chein-Wei Jen, Charng Long Lee

Journal:

Signal Processing: Image Communication

Year:

1994

Language:

english

File:

PDF, 1.40 MB

english, 1994

25

VASS—A VLSI array system synthesizer

Jinn-Wang Yeh, Wen-Jiunn Cheng, Chein-Wei Jen

Journal:

Journal of Signal Processing Systems

Year:

1996

Language:

english

File:

PDF, 1.83 MB

english, 1996

26

Edge-preserving texture filtering for real-time rendering

Yuan-Chung Lee, Chein-Wei Jen

Journal:

The Visual Computer

Year:

2003

Language:

english

File:

PDF, 567 KB

english, 2003

27

Improved quadratic normal vector interpolation for realistic shading

Yuan-Chung Lee, Chein-Wei Jen

Journal:

The Visual Computer

Year:

2001

Language:

english

File:

PDF, 904 KB

english, 2001

28

Architecture of full-search block matcing for minimum memory bandwidth requirement

Jen-Chien Tuan, Chein-Wei Jen

Journal:

Computer Standards & Interfaces

Year:

1999

Language:

english

File:

PDF, 79 KB

english, 1999

29

Simulatable timing model for MOS logic circuit

Shyh-Jye Jou,, Wen-Zen Shen,, Chein-Wei Jen,, Chung-Len Lee,

Journal:

IEE Proceedings G (Electronic Circuits and Systems)

Year:

1987

Language:

english

File:

PDF, 1.01 MB

english, 1987

30

Evident risk factors for younger stroke patients in Taiwan

Chein-Wei Chang, Huey-Jen Lay, Yi-Shiung Horng, Yau-Wai Wai, I-Nan Lien

Journal:

Journal of Stroke and Cerebrovascular Diseases

Year:

1995

Language:

english

File:

PDF, 529 KB

english, 1995

31

A low-cost raster engine for video game, multimedia PC and interactive TV

Chein-Liang Chen, Bor-Sung Liang, Chein-Wei Jen

Journal:

IEEE Transactions on Consumer Electronics

Year:

1995

Language:

english

File:

PDF, 589 KB

english, 1995

32

Low power design for MPEG-2 video decoder

Chia-Hsing Lin, Chen-Min Chen, Chein-Wei Jen

Journal:

IEEE Transactions on Consumer Electronics

Year:

1996

Language:

english

File:

PDF, 867 KB

english, 1996

33

A multiplierless reconfigurable resizer for multi-window image display

Ching-Mei Huang, Tian-Sheuan Chang, Chein-Wei Jen

Journal:

IEEE Transactions on Consumer Electronics

Year:

1997

Language:

english

File:

PDF, 862 KB

english, 1997

34

Computation-effective 3-D graphics rendering architecture for embedded multimedia system

Bor-Sung Liang, Chein-Wei Jen

Journal:

IEEE Transactions on Consumer Electronics

Year:

2000

Language:

english

File:

PDF, 854 KB

english, 2000

35

Optimal frame memory and data transfer scheme for MPEG-4 shape coding

Kun-Bin Lee, Hao-Yun Chin, Chang, N.Y.-C., Hui-Cheng Hsu, Chein-Wei Jen

Journal:

IEEE Transactions on Consumer Electronics

Year:

2004

Language:

english

File:

PDF, 908 KB

english, 2004

36

Generalized earliest-first fast addition algorithm

Wen-Chang Yeh, Chein-Wei Jen

Journal:

IEEE Transactions on Computers

Year:

2003

Language:

english

File:

PDF, 1.25 MB

english, 2003

37

Data flow representation of iterative algorithms for systolic arrays

Chein-Wei Jen, Ding-Ming Kwai

Journal:

IEEE Transactions on Computers

Year:

1992

Language:

english

File:

PDF, 429 KB

english, 1992

38

High-speed Booth encoded parallel multiplier design

Wen-Chang Yeh, Chein-Wei Jen

Journal:

IEEE Transactions on Computers

Year:

2000

Language:

english

File:

PDF, 1.24 MB

english, 2000

39

A New Array Architecture for Prime-Length Discrete Cosine Transform

Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen

Journal:

IEEE Transactions on Signal Processing

Year:

1993

Language:

english

File:

PDF, 562 KB

english, 1993

40

[IEEE 2000 International Conference on Acoustics, Speech and Signal Processing - Istanbul, Turkey (5-9 June 2000)] 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100) - A high performance carry-save to signed-digit recoder for fused addition-multiplication

Wen-Chang Yeh,, Chein-Wei Jen,

Year:

2000

Language:

english

File:

PDF, 237 KB

english, 2000

41

[IEEE 2003 IEEE Workshop on Signal Processing Systems - Seoul, South Korea (27-29 Aug. 2003)] 2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) - Optimal data transfer and buffering schemes for JPEG2000 encoder

Mu-Yu Chiu,, Kun-Bin Lee,, Chein-Wei Jen,

Year:

2003

Language:

english

File:

PDF, 373 KB

english, 2003

42

A simple processor core design for DCT/IDCT

Tian-Sheuan Chang,, Chin-Sheng Kung,, Chein-Wei Jen,

Journal:

IEEE Transactions on Circuits and Systems for Video Technology

Year:

2000

Language:

english

File:

PDF, 324 KB

english, 2000

43

[Widerkehr & Associates 1996 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (13-15 June 1996)] 1996 Symposium on VLSI Circuits. Digest of Technical Papers - The IDCT processor on the adder-based distributed arithmetic

Chingson Chen,, Tian Sheuan Chang,, Chein-Wei Jen,

Year:

1996

Language:

english

File:

PDF, 215 KB

english, 1996

44

Index rendering: hardware-efficient architecture for 3-D graphics in multimedia system

Bor-Sung Liang,, Yuan-Chung Lee,, Wen-Chang Yeh,, Chein-Wei Jen,

Journal:

IEEE Transactions on Multimedia

Year:

2002

Language:

english

File:

PDF, 642 KB

english, 2002

45

[IEEE International Symposium on VLSI Technology, Systems and Applications - Taipei, Taiwan (17-19 May 1989)] International Symposium on VLSI Technology, Systems and Applications - A bit-level scalable median filter using simple majority circuit

Charng Long Lee,, Chein-Wei Jen,

Year:

1989

Language:

english

File:

PDF, 558 KB

english, 1989

46

[IEEE ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 - Yohohama, Japan (27-30 Jan. 2004)] ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) - A bandwidth and memory efficient MPEG-4 shape encoder

Kun-Bin Lee,, Nelson Yen-Chung Chang,, Hao-Yun Chin,, Hui-Cheng Hsu,, Chein-Wei Jen,

Year:

2004

Language:

english

File:

PDF, 182 KB

english, 2004

47

[IEEE 1993 International Symposium on VLSI Technology, Systems, and Applications Technical Papers - Taipei, Taiwan (12-14 May 1993)] 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers - A two-level on-chip memory for video signal processor

Chia-Hsing Lin,, Jen-Sheng Hung,, Chein-Wei Jen,

Year:

1993

Language:

english

File:

PDF, 389 KB

english, 1993

48

[IEEE 1991 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan (22-24 May 1991)] 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers - The designs of two-level pipelined systolic arrays for recursive digital filters with maximum throughput rate

Shih-Chieh Wen,, Chi-Min Liu,, Chein-Wei Jen,

Year:

1991

Language:

english

File:

PDF, 330 KB

english, 1991

49

[IEEE 1993 International Symposium on VLSI Technology, Systems, and Applications Technical Papers - Taipei, Taiwan (12-14 May 1993)] 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers - A two-level pipelined systolic array chip for computing the discrete cosine transform

Jiun-In Guo,, Chi-Min Liu,, Chein-Wei Jen,

Year:

1993

Language:

english

File:

PDF, 325 KB

english, 1993

50

[IEEE Comput. Soc 21st International Conference on Computer Design - San Jose, CA, USA (13-15 Oct. 2003)] Proceedings 21st International Conference on Computer Design - An efficient VLIW DSP architecture for baseband processing

Tay-Jyi Lin,, Chin-Chi Chang,, Chen-Chia Lee,, Chein-Wei Jen,

Year:

2003

Language:

english

File:

PDF, 548 KB

english, 2003